Conventional analog to digital conversion circuits may include charge to voltage converters that typically comprise an operational amplifier (op amp) with an integrating capacitor connected between an inverting terminal and an output terminal of the operational amplifier. A linear relationship exists between an input charge applied at an input of the op amp and an output voltage of the operational amplifier when the operational amplifier operates within a characteristic active region. Characteristically, the operational amplifier is able to hold a finite amount of charge before the operational amplifier saturates and begins to display a non-linear relationship between the input charge and the output voltage. In analog to digital conversion circuits, linear operation of the operational amplifier is desired to accurately resolve the analog input signal into digital output bits. To accommodate a large range of input charges, integrate and fold circuitry has been proposed to effectively increase a dynamic range of the analog to digital conversion circuit while ensuring that the op amp is operated in a linear region so that a desired conversion accuracy is achieved.
An example of an charge to digital analog to digital converter using integrate and fold circuitry with saturation prevention is described in U.S. Pat. No. 6,366,231. Such analog to digital converters typically include multiple stages to achieve a desired degree of resolution, with each stage amplifying a folding residue from a previous stage. Folding in a conventional first stage is typically suspended to allow an output of the first stage to settle before allowing a residue to be sampled by a second stage. It is desired to reduce the settling time of the first stage to achieve faster conversion, but solutions such as increasing a bandwidth of a first stage op amp or increasing an integrating capacitor size requires an undesirable increase in power requirements and circuit area, respectively.
In second stage of a converter, amplification of the residue from the first stage is typically performed by first amplifying the residue with a sampling capacitor at the input of the second stage to produce a charge amplified residue. The charge amplified residue is then amplified via a feedback capacitor of a stage amplifying op amp to produce a stage amplified residue. Folding in the second stage is then accomplished by discharging a sampling capacitor into to the smaller feedback capacitor using a current source. The second stage folding process is partially governed by an resistor-capacitor (RC) time constant of the second stage as the current source degenerates into a resistor at low current levels near an end of a discharging cycle. As a result, the RC time constant determines a conversion rate of the second stage. In addition, because of time limitation imposed for folding in the first stage, a residue provided to the second stage may be relatively large, requiring a relatively large number of folds, and a corresponding large amount of time for performing the required folds in the second stage. A fold rate of such a second stage is typically limited by a bandwidth of the second stage op amp. Increasing a bandwidth of the second stage op amp may improve performance, but at the cost of an undesirable increase in power requirements. In diagnostic imaging equipment, such as in digital x-ray or computed-tomography (CT) systems, it is desired to increase conversion speed while reducing power requirements and reducing circuit size.